As devices become smaller and integration density increases, reactive ion etching (RIE) has become a key process in anisotropic etching of semiconductor features. RIE or ion-enhanced etching works by a combination of physical and chemical mechanisms for achieving selectivity and anisotropicity during the etching process. Generally, plasma assisted anisotropic etching operates in the milliTorr and above range. Generally three processes compete with each other during plasma etching; physical bombardment by ions, chemical etching by radicals and ions, and surface passivation by the deposition of passivating films. In some applications, for example, etching high aspect ratio features such as vias, high density plasma (HDP) etching which has a higher density of ions and operates at lower pressures has been increasingly used in etching high aspect ratio features, for example, with aspect ratios greater than about 3:1. One variable for increasing anisotropicity in etching high aspect ratio openings is to vary the RF power for altering the concentration of ions and radicals and to vary the bias power applied to the semiconductor wafer for varying the energy of the impacting ions and radicals.
During the formation of semiconductor devices it is often required that the conductive layers be interconnected through holes in an insulating layer also referred to as an inter-metal dielectric (IMD) layer. Such holes are commonly referred to as contact holes, i.e., when the hole extends through an insulating layer to an active device area, or vias, i.e., when the hole extends through an insulating layer between two conductive layers. The profile of a hole is of particular importance since that it exhibits specific electrical characteristics when the contact hole or via is filled with a conductive material. Typically, the holes are high aspect ratio holes, meaning that the ratio of length to width is greater than about 3. Such holes are typically formed by a reactive ion etching (RIE) process where complex chemical processes assisted by ion bombardment result in relatively higher etching rates in one direction versus another, known as anisotropic etching. The relative anisotropicity or selectivity of the etching process will in turn determine the etching profile of an etched hole and consequently its aspect ratio. As semiconductor structures are inevitably driven to smaller sizes, successful etching of higher aspect ratio holes is becoming more difficult.
In anisotropically etching contact or via holes (openings), plasmas containing fluorocarbons or hydrofluorocarbons including oxygen and nitrogen are typically optimized in various steps in a plasma etch process to selectively etch through the various layers of materials included in a multi-layered semiconductor device. For example, it is typically required to selectively etch through a metal nitride or silicon carbide layer forming the etching stop layer prior to etching the contact or via hole through the IMD layer while minimizing the etching of an overlying patterned photoresist layer. For example, plasmas containing fluorocarbons or hydrofluorocarbons such as CF4 and CHF3 are used to etch through the etching stop layer and more carbon rich hydrofluorocarbons such as C4F6 are used to etch through the etching stop layer and the inter-metal dielectric (IMD) layer. Using carbon-rich hydrofluorocarbons containing plasmas provides a means of selectively etching high aspect ratio contact and via holes through oxide layers such as an IMD layer while minimizing etching of the overlying hardmask or etching stop layer.
Another plasma process common in semiconductor manufacturing are plasma assisted chemical vapor deposition (CVD) assisted techniques, including PECVD and HDP-CVD. In particular, high density plasma (HDP) processes, such as electron cyclotron resonance (ECR) processes and induced coupling plasma (ICP) processes have been found to produce high-quality low dielectric constant (e.g., <3.0) carbon doped silicon oxide. Generally, HDP-CVD provides a high density of low energy ions resulting in higher quality films at lower deposition temperatures, compared to for example, PECVD. HDP-CVD is particularly ideal for forming inter-metal dielectric (IMD) insulating oxide layers because of its superior gap filling capability.
A common phenomena in multi-level semiconductor devices, for example, including 5 to 8 levels of dielectric insulating layers having metal filled interconnects such as vias or trench lines, is charge accumulation related to the various plasma assisted processes such as deposition and anisotropic etching. Depending on the various process parameters such as RF power and bias power, impacting ions and radical may cause the accumulation of charge within the dielectric insulating layers due to charge imbalances caused by non-uniformities in the plasma and charge non-uniformities caused by the etching target. For example, charged species may become incorporated within the surface of the layer, with localized charge accumulation aided by defects formed in the dielectric insulating layer. In addition, ion and radical bombardment may increase the concentration of charged defects at localized portions of the surface, thereby increasing localized charge buildup within the layer. As dielectric insulating layers have decreased in dielectric constant, their increased electrical insulating characteristics also contribute to the localized buildup of electrical charge within the insulating portion of the multi-level device. The electrical charge build-up is frequently long lasting, lasting at least for several hours.
One detrimental effect of the localized accumulation of charge in the dielectric insulating layer and exacerbated by non-uniformities in the plasma is exhibited during RIE etching processes, for example, in anisotropically etching vias. As previously mentioned, in achieving the required anisotropicity for high aspect ratio features a delicate balance between the concentration of ions and radicals and the energy of ion and radical bombardment is required. The problem of arcing or electrical discharge of the plasma to localized charged areas on the semiconductor wafer has increasingly become a critical problem in RIE processes. The increased incidence of arcing damage is believed to be related to the increased localization of unequal charge distribution in low dielectric constant insulating layers together with the plasma processing parameters necessary to achieve high aspect ratio anisotropic etching.
The arcing damage typically occurs in the vicinity of metallization line, believed to provide a pathway to localized charged areas in the dielectric insulating layer. The problem is critical since the damage caused by the arcing typically is typically severe and the extent of damage to underlying regions and surrounding areas not readily ascertainable making further processing of the wafer impractical. As a result, arcing damage to the wafer is costly in terms of wafer yield and reliability.
There is therefore a need in the semiconductor processing art to develop a method whereby plasma arcing is avoided during anisotropic etching of dielectric insulating layers thereby avoiding arcing induced defects to the semiconductor wafer to improve wafer yield and device reliability.
It is therefore an object of the invention to provide a method whereby plasma arcing is avoided during anisotropic etching of dielectric insulating layers thereby avoiding arcing induced defects to the semiconductor wafer to improve wafer yield and device reliability while overcoming other shortcomings and deficiencies of the prior art.